Method for fabricating a metal gate structure

ABSTRACT

A metal gate structure is disclosed. The metal gate structure includes: a semiconductor substrate having an active region and an isolation region; an isolation structure disposed in the isolation region; a first gate structure disposed on the active region; and a second gate structure disposed on the isolation structure, wherein the height of the second gate structure is different from the height of the first gate structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.12/101,160, filed on Apr. 11, 2008, and all benefits of such earlierapplication are hereby claimed for this new continuation application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a gatestructure, and more particularly, to a method of fabricating a metalgate structure.

2. Description of the Prior Art

With a trend towards scaling down the complementary metal oxidesemiconductor (CMOS) size, conventional methods used to achieveoptimization, such as reducing thickness of the gate dielectric layer,for example the thickness of silicon dioxide layer, have faced problemssuch as leakage current due to tunneling effect. In order to keepprogression to next generation, high-K materials are used to replace theconventional silicon oxide (SiO2) or silicon-oxy-nitride (SiON) to bethe gate dielectric layer because it decreases physical limit thicknesseffectively, reduces leakage current, and obtains equivalent capacitorin an identical equivalent oxide thickness (EOT).

Additionally, current metal-oxide-semiconductor field-effect transistors(MOSFETs) often utilize polysilicon to make a gate. A doped polysilicongate has problems, however, such as a depletion effect of thepolysilicon gate, and boron penetrates through the channel.

Take the depletion effect of the poly-silicon gate as an example. Whenthe polysilicon gate is in an inversion, carrier depletion occursbetween the polysilicon gate and the gate dielectric layer. If thispolysilicon gate has the afore-mentioned depletion effect, the effect ofthe gate capacitance will decrease, but a high quality metal oxidesemiconductor transistor (MOS transistor) should have a high gatecapacitance. If the gate capacitance is high, more electric charge willaccumulate in two sides of the gate capacitance. More electric chargetherefore accumulates in the channel, so when the metal oxidesemiconductor transistor (MOS transistor) has a bias voltage, the speedof the electric current between the source/drain will be improved.

To avoid the above-mentioned depletion effect and boron penetrates ofthe polysilicon gate; the current industry devotes to investigate intoutilizing a metal gate to replace the polysilicon gate, namely,utilizing metal materials to replace the polysilicon materials used inthe polysilicon gate, so as to resolve the aforesaid problems and alsoto decrease the resistivity of the gate.

Therefore, plenty of new metal materials have been found. For example,double work function metals are used to replace the conventionalpolysilicon gate to be the control electrode that competent to thehigh-K gate dielectric layer. Besides, critical requirements for thosemetal materials include thermal stability with the gate dielectric andsuitable values for the interfacial work function (˜4.0 eV and ˜5.0 eVfor bulk-Si NMOS and PMOS devices respectively). Accordingly, how tocombine those metal gates with the current manufacture process of theMOS transistors has become another important challenge for the currentindustry.

SUMMARY OF THE INVENTION

The present invention relates to a method of fabricating a gatestructure, and more particularly, to a method of fabricating a metalgate structure.

According to the claims of the present invention, a method offabricating a metal gate structure is provided. The method includesproviding a semiconductor substrate, the semiconductor substratedefining at least an isolation region and at least an active region;forming a polysilicon material on the semiconductor substrate;planarizing the polysilicon material to form a planarized polysiliconmaterial; patterned the planarized polysilicon material to form at leasta gate on the isolation region and the active region, respectively firstgate and a second gate on the semiconductor substrate, wherein the firstgate is located on the active region and the second gate at leastpartially overlaps with the isolation region; forming an inter-layerdielectric material covering the gates on the semiconductor substrate;planarizing the inter-layer dielectric material until exposing the gatesand forming an inter layer-dielectric layer; performing an etchingprocess to remove the gates to form a first recess and a second recesswithin the inter-layer dielectric layer; forming a gate dielectricmaterial on a surface of each of the recesses; forming at least a metalmaterial within the recesses; and performing a planarization process.

According to another aspect of the present invention, a metal gatestructure is disclosed. The metal gate structure includes: asemiconductor substrate having an active region and an isolation region;an isolation structure disposed in the isolation region; a first gatestructure disposed on the active region; and a second gate structuredisposed on the isolation structure, wherein the height of the secondgate structure is different from the height of the first gate structure.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 to FIG. 9 are cross-sectional diagrams illustrating a method offabricating a metal gate structure according to a first preferredembodiment of the present invention.

FIG. 10 to FIG. 13 are cross-sectional diagrams illustrating a method offabricating a metal gate structure according to a second preferredembodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 1 to FIG. 9, which are cross-sectional diagramsillustrating a method of fabricating a metal gate structure according toa first preferred embodiment of the present invention. As shown in FIG.1, at first, a semiconductor substrate 2 is provided such as a siliconsubstrate or a silicon-on-insulator (SOI) substrate, etc. At least anisolation region 12 such as shallow trench isolation (STI) or a fieldoxide (FOX) is formed within the semiconductor substrate 2. Theisolation region 12 is slightly higher than the surface of thesemiconductor substrate 2 due to the standard fabrication of theisolation regions. For example, the standard process of formingisolation region includes: forming a liner oxide layer and hard masklayer in sequence; patterning the hard mask layer, the liner oxidelayer, and the semiconductor substrate to form a trench within thesemiconductor substrate; filling the trench with dielectric materials;planarizing the dielectric materials until exposing the hard mask layer;finally removing the hard mask layer to form the shallow trenchisolation region 12. Next, a dielectric material 4 is formed on aportion surface of the semiconductor substrate 2, where the isolationregion 12 is not included in, i.e. an active region 14. Subsequently, apolysilicon material 16, which covers the isolation region 12 and thedielectric material 4, is formed on the semiconductor substrate 2. Ingeneral, the dielectric material 4 is composed of isolating materialssuch as silicon oxide components or silicon nitride components. Whilethe dielectric material 4 is silicon oxide components formed by thermaloxide growth process, it will grow selectively on the exposed siliconsubstrate. However, while the dielectric materials is composed of high-kdielectric materials formed by deposition process, it will cover thewhole semiconductor substrate including the isolation region 12 (notshown). Besides, the polysilicon material 16 may be doped polysiliconformed by in-situ or ex-situ doping process, or un-doped polysilicon. Itshould be noticed that at least an N-type transistor region and at leasta P-type transistor region may be defined on the active region 14 inaccordance with different functional transistors, such as NMOStransistors or PMOS transistors, which will be formed on the differentregions in the following processes (not shown); and doped wells may beformed in the suitable positions within the semiconductor substrate 2(not shown).

As shown in FIG. 2, a planarization process, such as a chemicalmechanical polish (CMP) process, is performed on the polysiliconmaterial 16, so as to form a planarized polysilicon material 18. A hardmask material 20 is then formed on the planarized polysilicon material18. The hard mask material 20 may be composed of silicon nitride (SiN),silicon oxide (SiO2), silicon oxy-nitride (SiON) with higheretching-selectivity to silicon.

As shown in FIG. 3, photolithographic processes and etching processesare performed to etch the hard mask material 20, planarized polysiliconmaterial 18, and the dielectric material 4, so as to form at least asecond gate 22, and a first gate 24 on the isolation region 12 and theactive region 14, respectively on semiconductor substrate 2, and hardmask layers 20 on the gate 22, 24, respectively. The first gate 24 onthe active region 14 includes a dielectric layer 4 on the semiconductorsubstrate 2 and a polysilicon layer 18 on the dielectric layer 4. Thesecond gate 22 comprises a polysilicon layer, which is formed by etchingthe planarized polysilicon material 18. Afterwards, an ion implantationprocess is performed to form lightly doped regions at the suitablepositions within the semiconductor substrate 2 (not shown). It should benoticed that the first gate 24 on the active region 24 may be an N-typegate or a P-type gate having different functions according to differentintegrated circuit designs (not shown). Furthermore, at least an N-typegate and at least a P-type gate (not shown) may be formed on the N-typetransistor region and the P-type transistor region (not shown),respectively according to different integrated circuit designs anddemands. In addition, the second gate 22 on the isolation region 12 ismay be an extended portion of a gate of an adjacent transistor, a bridgeportion between two gates of two adjacent transistors, an extendingportion of a gate for improving line-end shortening effect, or just alinear segment of non-polysilicon or polysilicon used just as aresistor. The second gate 22 is not limited to be set all on theisolation region 12, it may also be partially set across on a portion ofthe isolation region 12 and be partially set on a portion of the activeregion 14. It should be noticed that although the second gate 22 isdenominated “gate”, it is not necessary to have the structure and thefunctions of a transistor. The term of gate here only refers to apatterned non-polysilicon, polysilicon, or metal segment.

As shown in FIG. 4, deposition processes and etching processes areperformed to form spacers 34, 36 on sidewalls of the gates 22, 24 andthe hard mask layers 20 respectively, so as to form gate structures 38,40. Subsequently, at least an ion implantation process is performed toform heavily doped regions, which is prepared for each transistor asdemanded source/drain regions, at the suitable positions within thesemiconductor substrate 2 (not shown). A metal silicide process, such asself-aligned silicide (salicide) process, may be optionally carried outto form metal silicides on the source/drain regions or the regions,which need to be electrically connected with the other regions formed inthe following processes (not shown). This process is well known by thoseskilled in the art, and the details of which are not further explainedherein for the sake of brevity. It should be noticed that as the activeregions 14 includes at least an N-type gate and at least a P-type gate,thus an N-type gate structure and a P-type gate structure will be formedon the active region 14 after the deposition and the etching processesof forming spacers. Besides, the source/drain regions may be fabricatedby some technologies, such as selective epitaxial growth (SEG), etc, butis not limited thereto, that numerous modifications and alterations ofthe method may be made while retaining the teachings of the invention.Furthermore, if the second gate is used as a resistor, it is notnecessary to have the doped region and the metal silicide formed on thesecond gate.

Afterwards, a deposition process is performed to form a cap layer 42,which is composed of silicon nitride or carbide components, etc, on thesemiconductor substrate 2. Another deposition process is then performedto form an inter-layer dielectric (ILD) material, which is composed ofisolating materials such as silicon oxide components, etc. Subsequently,a planarization process such as a chemical mechanical polish (CMP)process is carried out to form a planarized inter-layer dielectric (ILD)layer 44 on the semiconductor substrate 2 as shown in FIG. 5.

As shown in FIG. 6, at least an etching process is carried out to removea portion of the cap layer 42, the hard mask layers 20, a portion of thespacers 34, 36, and a portion of the inter-layer dielectric (ILD) layer44 is removed by the dry etching or chemical mechanical polish (CMP)process until the gates second gate 22 and, the first gate 24 within thegate structures 38, 40 are exposed.

As shown in FIG. 7, at least an etching process, such as a dry or a wetetching process, is performed to remove the second gates 22, and thefirst gate 24 within the gate structures 38, 40, so as to formcorresponding recesses 46, 48 within the planarized inter-layerdielectric layer 44. If the gate structure 38 is used as the resistor,the second gate 22 needn't to be removed. Under the circumstance, thepolysilicon layer 18 may be selectively removed by covering the gatestructure 38 with the photoresist. The other method is to differentiatethe polysilicon layer of the gate structures 38 from the polysiliconlayer of the gate structure 40 using the different dopants. In addition,if the dielectric material 4 is an oxide layer fabricated by the thermaloxide growth process, it can be removed with the method as shown in FIG.7. However, if the dielectric material 4 is a high-K dielectricmaterial, which is fabricated by the deposition process, it can be leftfor replacing the gate dielectric material 54, which is desired to beformed in the following processes (not shown).

As shown in FIG. 8, at least a deposition process is carried out to forma gate dielectric material 54, which may further include some filmlayers such as a dielectric material 50 and a high-K dielectric material52, etc, covering the inter-layer dielectric (ILD) layer 44, a portionof the spacers 34, 36, the isolation region 12 within the recess 46, andthe semiconductor substrate 2 within the recess 48. However, the gatedielectric material 54 doesn't fill the recesses 46, 48. Afterwards, adeposition process is carried out to form a metal material 56, whichfills the recesses 46, 48.

It should be noticed that the deposition processes as shown in FIG. 8may vary with different integrated circuit designs and demands. Whenthere are at least an N-type gate structure and at least a P-type gatestructure formed on the active region 14, a recess will be formed withineach of the N-type and P-type gate structure, respectively, afterperforming the step as shown in FIG. 7 of removing the gates within thegate structures (not shown). Next, an N-type metal material is formed onthe semiconductor substrate 2 (not shown). The N-type metal materialdoesn't fill the recesses within the N-type and P-type gate structures.An etching process is then carried out to remove the N-type metalmaterial within the recess of the P-type gate structure. Subsequently, alow resistivity P-type metal material (not shown) is formed on thesemiconductor substrate 2 and the low resistivity P-type metal materialfills the recesses within the N-type and P-type gate structures.Finally, a planarization process as shown in FIG. 9 is performed, whichwill be described in detail later.

In addition, a low resistivity metal material (not shown) may be formedon the semiconductor substrate 2 after forming the N-type metalmaterial. The low resistivity metal material fills the recesses withinthe N-type and P-type gate structure. Therefore, while performing theetching process, both the N-type metal material and the low resistivitymetal material within the recess of the P-type gate structure must beremoved. Afterwards, a P-type metal material (not shown) is formed onthe semiconductor substrate 2. The P-type metal material doesn't fillthe recess within the P-type gate structure. Another low resistivitymetal material (not shown) is then formed on semiconductor substrate 2.The low resistivity metal material fills the recesses within the N-typeand the P-type gate structure. Finally, a planarization process as shownin FIG. 9 is carried out, which will be described in detail later.

Besides, it should also be noticed that the etching process and thedeposition processes of the metal materials as shown in FIG. 7 to FIG. 8are not limited to removing the N-type gate within the N-type gatestructure and the P-type gate within the P-type gate structuresimultaneously. The N-type gate within the N-type gate structure may beremoved first to form a recess (not shown) within the N-type gatestructure. A gate dielectric layer (not shown) is then formed on thesurface of the recess. Subsequently, the recess is directly filled withan N-type metal material (not shown). Afterwards, the P-type gate isremoved to form another recess (not shown) within the P-type gatestructure. Similarly, another gate dielectric layer (not shown) is thenformed on the surface of the recess. Subsequently, the recess isdirectly filled with a P-type metal material (not shown). Finally, aplanarization process as shown in FIG. 9 is carried out, which will bedescribed in detail later.

The aforesaid all kinds of methods of metal gate last fabrications areall not limited to carry out the steps of forming N-type gate before thesteps of P-type gate. Those methods may also carry out the steps ofP-type gate before the steps of N-type gate, etc, that numerousmodifications and alterations of the method may be made while retainingthe teachings of the invention. The first gate 24 and the second gate 22may both be N-type gates or may both be P-type gates. However, if one ofthe gates 22, 24 is N-type and the other is P-type may also be used aswell.

According to the preferred embodiment of the present invention, theaforesaid P-type metal materials include titanium nitride (TiN),tungsten (W), tungsten nitride (WN), molybdenum nitride (MoN), andmolybdenum aluminum nitride (MoAlN), platinum (Pt), nickel (Ni), andRuthenium (Ru), etc. The aforesaid N-type metal materials includetitanium aluminum nitride (TiAlN), tantalum carbide (TaC), and tantalumnitride (TaN), tantalum silicon nitride (TaSiN), and titanium aluminide(TiAl), etc. Furthermore, the aforesaid low resistivity metal materialsinclude titanium aluminide (TiAl), aluminum (Al), tungsten (W), andcobalt tungsten phosphide (CoWP), etc.

Finally, at least a planarization process, such as chemical mechanicalpolishing (CMP) process, is performed to completely removed the metalmaterial 56, gate dielectric material 54 disposed above the inter-layerdielectric (ILD) layer 44. As a result, second metal gate structures 66,and the first metal gate stricture 68 are formed on the isolation region12 and the active region 14, respectively, as shown in FIG. 9. Thesecond metal gate structure 66 includes a gate dielectric layer 58 and ametal layer 62; and the first metal gate structure 68 includes a gatedielectric layer 60 and a metal layer 64.

Please refer to FIG. 10 to FIG. 13, which are cross-sectional diagramsillustrating a second preferred embodiment of the present invention,where like elements, regions, or layers are designated with likenumerals as shown in the first preferred embodiment described above. Asshown in FIG. 10, at first, a semiconductor substrate 2 is provided suchas a silicon substrate or a silicon-on-insulator (SOI) substrate, etc. Adielectric material 4, a first polysilicon material 6, and a siliconnitride material 8 are then formed on the semiconductor substrate 2 insequence. Subsequently, photolithographic processes and etchingprocesses are performed to etch through a portion of the hard mask layer8, such as the silicon nitride material 8, first polysilicon material 6,dielectric material 4, and to etch a portion of the semiconductorsubstrate 2, are patterned so as to form a trench 10 in thesemiconductor substrate 2.

Next, the trench 10 is filled with an isolating material, such assilicon oxide component or silicon nitride component. At least aplanarization process such as a chemical mechanical polishing (CMP)process, which uses the silicon nitride hard mask material 8 as aplanarizing stop layer, is performed. The hard mask silicon nitridematerial 8 is then removed. Therefore an isolation region 12 is formedwithin the trench 10 as shown in FIG. 11. Among which, a portion of thesemiconductor substrate 2, where the isolation region 12 is not includedin, is defined as an active region 14. Afterwards, a plurality of ionimplantation processes, such as well implantation processes, or channelimplantation processes, etc, may be carried out to form the demandeddoped regions, such as N-type well regions and P-type well regions, soas to define at least an N-type transistor region and at least a P-typetransistor region (not shown).

As shown in FIG. 12, a second polysilicon material 17 is formed on thefirst polysilicon material 16; and a hard mask material 20 is formed onthe second polysilicon material 17. It should be notice that first andsecond polysilicon material 6, 17 may be doped polysilicons formed byin-situ or ex-situ doping process, or un-doped polysilicons. Besides,the hard mask materials 8, 20 may be composed of silicon nitride (SiN),silicon oxy-nitride (SiON), or silicon carbide (SiC) with higheretching-selectivity to silicon.

As shown in FIG. 13, photolithographic processes and etching processesare performed to etch the hard mask material 20, the second polysiliconmaterial 17, and the dielectric material 4, so as to form at least asecond gate 22 and a first gate 24 on the semiconductor substrate 2 onthe isolation region 12 and at least a gate 24 on the active region 14,so as to form at least a gate 22, 24 on the isolation region 12 and theactive region 14, respectively, and hard mask layers 20 on the gates 22,24, respectively. Among which, the first gate 24 is on the active region14 and the second gate 22 is at least partially across on the isolationregion 12. The first gate 24 on the active region 14 includes adielectric layer 4 on the semiconductor substrate 2, a first polysiliconlayer 6 on the dielectric layer 4, and a second polysilicon layer 33 onthe first polysilicon layer 6. The second gate 22 comprises apolysilicon layer 18, which is formed by etching the second polysiliconmaterial 17.

Afterwards, an ion implantation process is performed to form lightlydoped regions at the suitable positions within the semiconductorsubstrate 2 (not shown). It should be noticed that the gate 24 on theactive region 24 may be an N-type gate or a P-type gate having differentfunctions according to different integrated circuit designs (not shown).Furthermore, at least an N-type gate and at least a P-type gate (notshown) may be formed on the N-type transistor region and the P-typetransistor region (not shown), respectively according to differentintegrated circuit designs and demands. In addition, the second gate 22on the isolation region 12 is an extended portion of a gate of anadjacent transistor, a bridge portion between two gates of two adjacenttransistors, an extending portion of a gate for improving line-endshortening effect, or just a linear segment of non-polysilicon orpolysilicon used just as a resistor. The second gate 22 is not limitedto be set all on the isolation region 12; it may also be set both acrosson a portion of the isolation region 12 and a portion of the activeregion 14. It should be noticed that although the second gate 22 isdenominated “gate”, it is not necessary to have the structure and thefunctions of a transistor. The term of gate here only refers to apatterned non-polysilicon, polysilicon, or metal segment.

Subsequently, the processes the same as those shown in FIG. 4 to FIG. 9are performed. Finally, with the same result as shown in FIG. 9, asecond metal gate structure 66, and a first metal gate structures 66, 68are formed on the isolation region 12 and the active region 14,respectively. The second metal gate structure 66 includes a gatedielectric layer 58 and a metal layer 62; and the first metal gatestructure 68 includes a gate dielectric layer 60 and a metal layer 64.The details of which are not further described herein for the sake ofbrevity.

The present invention provides a method of fabricating a gate structure,and more particularly, to a method of fabricating a metal gatestructure. The method combines the metal gate with the currentmanufacture process of the MOS transistor. Therefore, a MOS transistorhaving the advantages of a metal gate, which overcomes the problems of apolysilicon gate such as a depletion effect, and boron penetratesthrough the channel, etc, is obtained by the conventional fabricationtechnology. Additionally, in the first preferred embodiment of thepresent invention, a planarization process is carried out to form aplanarized polysilicon layer before forming the gate; therefore, theheight of the gate on the isolation region and the height of the gate onthe active region are substantially the same. Furthermore, in the secondpreferred embodiment of the present invention, another polysiliconmaterial is used to achieve the same result described above.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A metal gate structure, comprising: a semiconductor substrate havingan active region and an isolation region; an isolation structuredisposed in the isolation region; a first gate structure disposed in theactive region; and a second gate structure disposed on the isolationstructure, wherein the height of the second gate structure is differentfrom the height of the first gate structure.
 2. The metal gate structureof claim 1, wherein the isolation structure comprises a shallow trenchisolation (STI) or a field oxide (FOX).
 3. The metal gate structure ofclaim 1, further comprising a first spacer around the first gatestructure.
 4. The metal gate structure of claim 1, further comprising asecond spacer around the second gate structure and above the isolationstructure.
 5. The metal gate structure of claim 1, wherein the firstgate structure comprises a first gate dielectric layer and a first metallayer.
 6. The metal gate structure of claim 5, wherein the first gatedielectric layer comprises a first dielectric material and a high-kdielectric material.
 7. The metal gate structure of claim 5, wherein thefirst metal layer comprises an N-type metal material or a P-type metalmaterial.
 8. The metal gate structure of claim 7, wherein the N-typemetal material comprises titanium aluminum nitride (TiAlN), tantalumcarbide (TaC), tantalum nitride (TaN), or an arbitrary combination oftitanium aluminum nitride (TiAlN), tantalum carbide (TaC), and tantalumnitride (TaN).
 9. The metal gate structure of claim 7, wherein theP-type metal material comprises titanium nitride (TiN), tungsten (W),tungsten nitride (WN), molybdenum nitride (MoN), molybdenum aluminumnitride (MoAlN), or an arbitrary combination of titanium nitride (TiN),tungsten (W), tungsten nitride (WN), molybdenum nitride (MoN), andmolybdenum aluminum nitride (MoAlN).
 10. The metal gate structure ofclaim 1, wherein the second gate structure comprises a second gatedielectric layer and a second metal layer.
 11. The metal gate structureof claim 10, wherein the second gate dielectric layer comprises adielectric material and a high-k dielectric material.
 12. The metal gatestructure of claim 10, wherein the second metal layer comprises anN-type metal material or a P-type metal material.
 13. The metal gatestructure of claim 12, wherein the N-type metal material comprisestitanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalumnitride (TaN), or an arbitrary combination of titanium aluminum nitride(TiAlN), tantalum carbide (TaC), and tantalum nitride (TaN).
 14. Themetal gate structure of claim 12, wherein the P-type metal materialcomprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN),molybdenum nitride (MoN), molybdenum aluminum nitride (MoAlN), or anarbitrary combination of titanium nitride (TiN), tungsten (W), tungstennitride (WN), molybdenum nitride (MoN), and molybdenum aluminum nitride(MoAlN).